1. Technical Field
The present invention relates generally to processors and computing systems, and more particularly, to a processor having branch prediction mechanisms, in which the depth of instruction buffers for predicted and non-predicted branches are dynamically adjusted.
2. Description of the Related Art
Present-day high-performance microprocessors include an instruction fetch unit (IFU) that fetches, decodes and dispatches instructions for execution by other processor core functional units. Instruction streams are sequentially fetched until execution is re-directed. A common example of such re-direction is a branch instruction. The branch may be “taken”, which causes a non-sequential fetch, or “not taken”, in which instruction fetching continues past the branch instruction. In a branch-predicting processor, instruction streams are pre-fetched according to a prediction of whether a branch will be “taken” or “not taken”. Various mechanisms have been used to determine whether a branch will be taken to ensure that the correct path is fetched. When a branch instruction is predicted as “taken”, the current instruction fetch path is re-directed to a new target address, and the instruction fetching proceeds linearly from the new target address. When the branch instruction is predicted as “not taken”, the instruction fetching is not redirected.
As instructions are fetched, they are typically stored in an instruction buffer (IB). Instructions are then removed from the IB, decoded and then sent to an instruction dispatch unit (IDU), which dispatches the instructions for execution by various functional units within the processor. When a branch instruction is executed, a branch processing unit (BU) determines whether or not the branch path was predicted correctly, and if the prediction was correct, no interruption in instruction sequence occurs. However, if the branch was mis-predicted, the current fetch path must be abandoned and the sequence of execution re-directed to the non-predicted branch path. Several penalties are incurred, including the time required to redirect the instruction sequence, the time required to flush the mis-predicted entries, and the power and thread resources wasted on fetching and preparing to execute the instructions on the mis-predicted path.
The amount of resources and processing power wasted on mis-prediction can be reduced by disabling predictive execution and stalling the pipeline pending resolution of each branch instruction. However, such behavior negates the advantage provided by branch prediction, that of providing a full instruction pipeline for full processor performance, with the pipeline being correctly filled most of the time.
It is therefore desirable to provide a methodology and a microprocessor that reduce the amount of resources and energy wasted on branch mis-prediction, while keeping the instruction pipeline full for full processing performance.